Semiconductor diode and method of manufacture

ABSTRACT

A diode ( 200 ) is disclosed having improved efficiency, smaller form factor, and reduced reverse biased leakage current. Schottky diodes ( 212 ) are formed on the sidewalls ( 210 ) of a mesa region ( 206 ). The mesa region ( 206 ) is a cathode of the Schottky diode ( 212 ). The current path through the mesa region ( 206 ) has a lateral and a vertical current path. The diode ( 200 ) further comprises a MOS structure ( 214 ), p-type regions ( 220 ), MOS structures ( 230 ), and p-type regions ( 232 ). MOS structure ( 214 ) with the p-type regions ( 220 ) pinch-off the lateral current path under reverse bias conditions. P-type regions ( 220 ), MOS structures ( 230 ), and p-type regions ( 232 ) each pinch-off the vertical current path under reverse bias conditions. MOS structure ( 214 ) and MOS structures ( 230 ) reduce resistance of the lateral and vertical current path under forward bias conditions. The mesa region ( 206 ) can have a uniform or non-uniform doping concentration.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is a divisional application of prior U.S. patentapplication Ser. No. 13/109,906, filed on May 17, 2011 and issued asU.S. Pat. No. 8,502,336 on Aug., 6, 2013, which is hereby incorporatedby reference, and priority thereto is hereby claimed.

BACKGROUND

This present invention relates, in general, to electronics, and moreparticularly, to semiconductor device structure and methods of formingthe device structure. Diodes are a common type of semiconductorcomponent that are used in both discrete and integrated forms.Semiconductor diodes conduct current when a positive voltage is appliedfrom an anode to a cathode of the device. Conversely, diodes arenon-conductive when a negative voltage is applied from the anode to thecathode. A common application for a diode is to rectify a signal. Inparticular, a diode is often used in the secondary side of switchingpower supplies. In this application, the diode is in the main powersupply path coupled for delivering power to a load. Thus, the rectifyingdiode can conduct substantial currents when coupled to the load andstorage device under regulation. The rectifying diode has a secondfunction. The diode prevents current conduction from the load when thesecondary winding of the transformer reverses polarity. The differencebetween the load voltage and secondary winding voltage can besubstantial depending on the application.

The rectifying diode affects power supply efficiency. The principal lossis associated with the forward voltage drop of the rectifier diodeduring the conducting portion of a switching power supply operatingcycle. The trade-off for increasing the size of the rectifying diode toreduce the forward voltage drop is to raise switching and leakagelosses. Utilizing a Schottky diode as the rectifying diode lowers theforward voltage drop thereby improving operating efficiency. It is alsoimportant that the leakage current under reverse bias conditions bemaintained or reduced when compared to other competing technologies. Ahigh leakage current degrades operating efficiency thereby reducing theadvantage of the low forward voltage drop of the Schottky diode.

Accordingly, it would be advantageous to have a diode having reducedleakage current under reverse bias conditions and a low forward voltagedrop under forward bias conditions. The advantages could be used tooptimize device operating efficiency, form factor, or both. It would beof further advantage if the method of manufacture of the device reducescomplexity, time, and cost to produce the diode.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of present invention will become more fully understood fromthe detailed description and the accompanying drawings, wherein:

FIG. 1 illustrates a switching power supply having an output rectifierin accordance with an example embodiment;

FIG. 2 illustrates a cross-sectional view of a diode in accordance withan example embodiment;

FIG. 3 illustrates a cross-sectional view showing current flow of thediode under forward biased conditions in accordance with an exampleembodiment;

FIG. 4 illustrates a cross-sectional view of a first pinch-off regionand a second pinch-off region when the diode is reverse biased inaccordance with an example embodiment;

FIG. 5 illustrates a cross-sectional view of a third pinch off regionand a fourth pinch-off region when the diode is reverse biased inaccordance with an example embodiment;

FIG. 6 illustrates a cross-sectional view of trenches formed inaccordance with an example embodiment of a diode;

FIG. 7 illustrates the diode at another stage of formation according toan example of the cross-sectional view of the preparation of thesidewalls;

FIG. 8 illustrates the diode at another stage of formation according toan example of the cross-sectional view of the preparation of extendingthe trenches;

FIG. 9 illustrates the diode at another stage of formation according toan example of the cross-sectional view having partially filled trenches;

FIG. 10 illustrates the diode at another stage of formation according toan example of the cross-sectional view of p-type regions formed in mesaregions; and

FIG. 11 illustrates the diode at another stage of formation according toan example of the cross-sectional view of Schottky diodes being formed.

DETAILED DESCRIPTION

The following description of embodiment(s) is merely illustrative innature and is in no way intended to limit the invention, itsapplication, or uses.

For simplicity and clarity of the illustration(s), elements in thefigures are not necessarily to scale, are only schematic and arenon-limiting, and the same reference numbers in different figures denotethe same elements, unless stated otherwise. Additionally, descriptionsand details of well-known steps and elements are omitted for simplicityof the description. As used herein current carrying electrode means anelement of a device that carries current through the device such as asource or a drain of an MOS transistor or an emitter or a collector of abipolar transistor or a cathode or anode of a diode, and a controlelectrode means an element of the device that controls current flowthrough the device such as a gate of an MOS transistor or a base of abipolar transistor. Although the devices may be explained herein ascertain N-channel or P-Channel devices, or certain N-type or P-typedoped regions, a person of ordinary skill in the art will appreciatethat complementary devices are also possible.

It will be appreciated by those skilled in the art that the words“during”, “while”, and “when” as used herein relating to circuitoperation are not exact terms that mean an action takes place instantlyupon an initiating action but that there may be some small butreasonable delay, such as a propagation delay, between the reaction thatis initiated by the initial action. Additionally, the term “while” meansthat a certain action occurs at least within some portion of a durationof the initiating action. The use of the word “approximately” or“substantially” means that a value of an element has a parameter that isexpected to be close to a stated value or position. However, as is wellknown in the art there are always minor variances that prevent thevalues or positions from being exactly as stated. It is well establishedin the art that variances of up to at least ten percent (10%) (and up totwenty percent (20%) for semiconductor doping concentrations) arereasonable variances from the ideal goal of exactly as described. Whenused in reference to a state of a signal, the term “asserted” means anactive state of the signal and inactive means an inactive state of thesignal. The actual voltage value or logic state (such as a “1” or a “0”)of the signal depends on whether positive or negative logic is used.Thus, “asserted” can be either a high voltage or a high logic or a lowvoltage or low logic depending on whether positive or negative logic isused and negated may be either a low voltage or low state or a highvoltage or high logic depending on whether positive or negative logic isused. Herein, a positive logic convention is used, but those skilled inthe art understand that a negative logic convention could also be used.

The terms “first”, “second”, “third” and the like in the Claims or/andin the Detailed Description are used for distinguishing between similarelements and not necessarily for describing a sequence, eithertemporally, spatially, in ranking or in any other manner. It is to beunderstood that the terms so used are interchangeable under appropriatecircumstances and that the embodiments described herein are capable ofoperation in other sequences than described or illustrated herein. Forclarity of the drawings, doped regions of device structures areillustrated as having generally straight line edges and precise angularcorners. However, those skilled in the art understand that due to thediffusion and activation of dopants the edges of doped regions generallymay not be straight lines and the corners may not be precise angles.

In addition, the description illustrates a cellular design (where thebody regions are a plurality of cellular regions) instead of a singlebody design (where the body region is comprised of a single regionformed in an elongated pattern, typically in a serpentine pattern).However, it is intended that the description is applicable to both acellular implementation and a single base implementation.

Processes, techniques, apparatus, and materials as known by one ofordinary skill in the art may not be discussed in detail but areintended to be part of the enabling description where appropriate. Forexample specific methods of semiconductor doping or etching may not belisted for achieving each of the steps discussed, however one ofordinary skill would be able, without undo experimentation, to establishthe steps using the enabling disclosure herein.

Notice that similar reference numerals and letters refer to similaritems in the following figures, and thus once an item is defined in onefigure, it may not be discussed or further defined in the followingfigures.

FIG. 1 is an illustration of a switching power supply 100 having anoutput rectifier 102 in accordance with an exemplary embodiment.Switching power supply 100 is represents a common configurationcomprising two stages of control. A first stage is a power factorcorrection (PFC) stage 104 and a second stage is a pulse widthmodulating (PWM) stage 106. In general, stages 104 and 106 provide bothpower factor correction and output voltage regulation of the switchingpower supply 100 through active adjustments based on detected input andoutput conditions. In the example, switching power supply 100 couples toan AC voltage, which is rectified, filtered, and provided to the PFCstage 104 as an input voltage. PFC stage 104 generates a regulatedvoltage that can differ from the output voltage of power supply 100. PFCstage 104 regulates by enabling and disabling a switch. As shown, theswitch is a transistor that is controlled by a power factor correctioncontroller circuit that adjusts a duty cycle of the enabled switch inresponse to a signal corresponding to the regulated output voltage ofstage 104. More specifically, power factor correction makes adjustmentsto maintain an input current having a relationship in time and amplitudewith the rectified input voltage provided thereto and with the outputcurrent drawn therefrom. The power factor correction circuitry typicallykeeps the power factor as close to unity as possible.

A second stage of switching power supply 100 is a pulse width modulating(PWM) stage 106. PWM stage 106 receives the regulated output voltage ofPFC stage 104 and drives transformer 108 to generate a regulated outputvoltage that differs from the regulated output voltage from stage 104.PWM stage 106 comprises pulse-width modulating control circuitry, aswitch, and a transformer. As shown, the switch is a transistor. Thepulse-width modulating control circuitry enables and disables the switchbased on an error signal. The error signal corresponds to a differencein the expected regulated output voltage of switching power supply 100and the voltage Vout at output 112. The voltage Vout at output 112 ofswitching power supply 100 varies over time due to the load andvariations in the load. For example, if the loading on output 112increases, the PWM stage 106 detects the change and responds by raisingthe duty cycle to deliver power to the load and maintain or increase thevoltage Vout. Conversely, the PWM stage 106 under reduced loading willlower the duty cycle to maintain regulation. In general, the stages 104and 106 will maintain the voltage at output 112 within a predeterminedvoltage range dictated by the power supply application.

The regulated output voltage of PFC stage 104 is impressed upon thetransformer 108 primary winding by PWM stage 106 in the first portion ofa switching cycle. In the second portion of a switching cycle, PWM stage106 discontinues impression of the regulated PFC output voltage on thetransformer primary winding and the transformer secondary windingconducts current through output rectifier 102 to the load. In theexample, output rectifier 102 is a rectifier diode having an anodecoupled to a secondary transformer winding and a cathode to the output112. A storage capacitor 110 is coupled to output 112 to provide powerto the load when not being delivered by stages 104 and 106. A resistordivider generates a voltage corresponding to the voltage at output 112that is used to monitor changes. As shown, the changes in voltage acrossthe resistor divider generate an error signal that is coupled opticallyto the pulse width modulating control circuitry.

The output rectifier 102 has two modes of operation in the switchingpower supply 100. In a first mode of operation, the output rectifier 102is in a high current path for driving the load coupled to the output 112of switching power supply 100. The output rectifier 102 couples PFCstage 104 and PWM stage 106 to the load through transformer 108 when theoutput rectifier 102 is forward biased. A forward biased conditionoccurs when the voltage at the anode of output rectifier 102 is greaterthan the voltage at the cathode. The amount of current handled by outputrectifier 102 can be significant depending on the application. Forexample, output rectifier 102 can conduct amperes to tens of amperes ofcurrent for high power switching power supply applications.

In a second mode of operation, output 112 is isolated by outputrectifier 102 from PFC stage 104, PWM stage 106, and transformer 108.The isolation is achieved when a voltage at the cathode of outputrectifier 102 is greater than a voltage at the anode of output rectifier102. In general, the output rectifier 102 is reverse biased under thiscondition and does not conduct current. As mentioned previously, thestorage capacitor 110 coupled to the output Vout delivers power to theload in the second mode of operation. The output rectifier 102 can standoff significant voltages while maintaining isolation between the output112 and the regulation circuitry. For example, the reverse bias voltageacross output rectifier 102 can be tens of volts to hundreds of voltsdepending on the application.

The output rectifier 102 is a contributor to the overall efficiency andcost of the switching power supply 100. In one embodiment, the outputrectifier 102 is a diode. More specifically, the output rectifier 102includes a Schottky diode. In the first mode of operation, the outputrectifier 102 can conduct a large current in providing power to the loadand charging the storage capacitor coupled to the output Vout. Theoutput rectifier 102 dissipates power while conducting the largecurrents to the load and storage capacitor. The power loss due to outputrectifier 102 corresponds to the forward voltage drop across the outputrectifier and the current flowing therethrough. The Schottky diodeimproves operating efficiency when compared to a silicon p-n diode dueto a lower forward voltage drop at a given operating current.

A second factor affecting the efficiency of switching power supply 100is leakage current from output rectifier 102 under reverse biasedconditions. The output rectifier 102 is required to standoff apredetermined voltage without breaking down. Typically, the leakagecurrent will rise as the reverse bias voltage increases. The power lossassociated with the leakage current corresponds to the voltage acrossthe output rectifier 102 and the leakage current. Optimization of theoutput rectifier 102 requires that both the leakage current and theforward voltage drop be taken into account to render an optimal minimumfor a power efficient rectifier.

It should be noted that the switching power supply 100 is used to merelyillustrate the general operation of output rectifier 102. Furthermore,the description above is an example of how the output rectifierinfluences the power efficiency of the power supply 100. There are manytypes of power supplies using secondary side output rectification. Highvolume commercial applications include low cost flyback circuits,notebook computer power supplies, and ATX power supplies all of whichwould benefit from an improved output rectifier. Cost and performanceare a factor in the selection of the technology used. Often, the initialcost of the supply is chosen over the most efficient solution eventhough improved efficiency yields a lower cost long term due to reducedenergy usage. The rectifier diode disclosed hereinbelow is applicable toall switching power supplies and other diode applications requiring lowforward voltage operation, high current capability, low current leakage,and high voltage breakdown.

Disclosed herein is a rectifier diode structure that results in asubstantial net performance improvement. As with most device structures,the performance can be traded off to improve one or more specific deviceparameters. The benefits of the device structure are numerous. Thedevice improves switching times, temperature stability, and provideshigher avalanche capabilities when compared to planar Schottkyrectifiers and MOSFET rectifiers having the same voltage and currentrating. In general, the disclosed Schottky rectifier diode reduces boththe forward voltage and leakage current in a trench structure. In onetrade-off embodiment, the parameters such as leakage current and forwardvoltage drop are held constant at a level that is commensurate with thebest in class rectifiers. The structure disclosed below is thenoptimized for silicon area resulting in a 30% reduction in siliconfootprint. Thus, the structure can be manufactured at lower cost withoutsacrificing other performance parameters thereby promoting theproliferation of more efficient power supplies at substantial long-termenergy reduction. Alternatively, the structure can be optimized forother performance parameters depending on the needs of the application.Moreover, the performance and cost improvements do not add complexity tothe power supply circuitry nor introduce changes in an assembly process.In other words, a performance improvement can be achieved by merelyreplacing the existing rectifier with the device disclosed hereinbelowallowing rapid retrofitting for lowering cost, improving performance, orboth.

FIG. 2 illustrates a cross-sectional view of a diode 200 in accordancewith an example embodiment. In general, a cathode region 204 of diode200 can be formed in a substrate 202 in regions or layers overlyingsubstrate 202. In the example, diode 200 is formed in a region or layeroverlying an n-type substrate 202 having a same conductivity type. Asdisclosed herein, a description of cathode region 204 being formed in asubstrate can include layers overlying the substrate. In one embodiment,n-type substrate 202 is a low resistivity n-type silicon substrate.Cathode region 204 of diode 200 diode is formed in a region or layerhaving a different resistivity than substrate. More specifically,cathode region 204 is n-type and has a resistivity that is greater thanthe substrate 202. The resistivity of the cathode region 204 supportsthe specified breakdown voltage of diode 200. The resistivity of thecathode region 204 can be uniform or non-uniform throughout a conductivepath. For example, the cathode region 204 can formed from a singleuniformly doped epitaxial layer. Dopant can be added at different depthsof the epitaxial layer to change the doping concentration in apredetermined fashion. Alternatively, more than one epitaxial layer maybe formed overlying the substrate 202. The different epitaxial layerscan have different doping concentrations to optimize performance of thecathode region 204 and devices formed therein while meeting the voltagebreakdown specification of diode 200 under reverse biased conditions. Asshown, cathode 204 comprises a single epitaxial layer overlyingsubstrate 202.

An n-type mesa region 206 can be formed for diode 200. The mesa region206 may be formed by a trench etch. The mesa region 206 comprises amajor surface 208 and sidewalls 210. The x and z-directions are shown inthe cross-section. The y-direction of the diode 200 extends to apredetermined length that corresponds to the device area. For example,the device area can comprise the junction area of diode 200. The devicearea may be determined by the performance requirements of diode 200 fora specific or general range of applications. In general, more than onemesa region can be formed in cathode region 204 for a high voltage andhigh current rectifier. Each mesa region can contain a diode having apredetermined device area. The anodes of each diode can be coupled incommon by a low resistance interconnect. The cathodes of each diode canshare cathode region 204 that can be coupled to the low resistivitysubstrate 202. In one embodiment, a metal layer can be formed on theexposed major surface of substrate 202 as a cathode contact for diode200.

In the example, the device structure is described hereinafter in threeregions. A first region comprises a portion of diode 200 abovehorizontal dashed line 222. A second region is the portion of diode 200below horizontal dashed line 222 and above horizontal dashed line 224. Athird region is the portion of diode 200 below horizontal dashed line224. In general, adjacent regions are merged such that the regions canaffect each other but are described separately to illustrate operationof the device. Operation of diode 200 under forward and reverse voltagebias conditions will be discussed in subsequent figures. It should benoted that additional regions using the principals outlined hereinaftermay be added to further enhance device performance.

In the first region of diode 200 above dashed line 222, a Schottky diode212 can be formed in sidewalls 210 of mesa region 206. The Schottkydiode 212 is a majority carrier device capable of operating at highspeeds. Schottky diode 212 includes a barrier metal 234 as the anodethat can be a formed layer on at least a portion of the sidewalls 210 ofmesa region 206. The cathode of Schottky diode 212 is the mesa region206. The anode and cathode of Schottky diode 212 respectively couple tothe anode and cathode of diode 200. Schottky diode 212 has a low forwardvoltage drop to improve power efficiency when used as a rectifying diodefor a switching power supply. As shown, the Schottky diode 212 is formedadjacent to the major surface 208 of mesa region 206. The active area ofSchottky diode 212 comprises barrier metal 234 coupling to bothsidewalls 210 of mesa region 206.

A MOS structure 214 can be formed overlying the major surface of mesaregion 206. An insulator layer 216 overlies the major surface of mesaregion 206. Insulator layer 216 may be an oxide or other type ofinsulator. A gate 218 is formed overlying insulator layer 216. In oneembodiment, gate 218 may be coupled to the anode of Schottky diode 212.Gate 218 comprises an electrically conductive material such as dopedpolysilicon, silicided polysilicon, a metal, or a combination thereof.In general, MOS structure 214 forms an enhancement region underlying themajor surface 208 of mesa region 206 when diode 200 is forward biased.Conversely, MOS structure 214 forms a depletion region underlying themajor surface 208 of mesa region 206 when diode 200 is reverse biased.

P-type regions 220 can be formed in the sidewalls 210 of mesa region206. In one embodiment, p-type regions 220 can be formed adjacent toSchottky diode 212 a predetermined distance below the major surface 208of mesa region 206. P-type regions 220 at the predetermined distancebelow the major surface 208 can bound Schottky diode 212 therebyreducing leakage current of Schottky diode 212. In the illustration,p-type regions are a lower boundary of Schottky diode 212. P-typeregions 220 are formed in mesa region 206 and extend a predetermineddistance from sidewalls 210. P-type regions 220 and n-type mesa region206 respectively comprise an anode and cathode of a p-n diode 221. Diode221 can be coupled in parallel with Schottky diode 212. In the example,the anode and cathode of p-n diode 221 respectively couple to the anodeand cathode of diode 200. A first forward biased operating condition ofdiode 200 corresponds to a majority of the current of diode 200 beingconducted by Schottky diode 212. The first operating condition typicallyoccurs under low current and mid current levels of diode 200. The lowforward voltage drop of Schottky diode 212 under low and mid currentlevels prevents diode 221 from conducting significant currents. A secondforward biased operating condition of diode 200 corresponds to acondition where Schottky diode 212 and p-n diode 221 conducting current.The second operating condition typically occurs when diode 200 conductshigh currents. The forward voltage drop of diode 200 under high currentscan forward bias p-n diode 221 for conducting a portion of the totalcurrent conducted by diode 200.

MOS structures 230 can be formed overlying sidewalls 210 of mesa region206 in the second region of diode 200 that resides above dashed line 224and below dashed line 222. An insulator layer 226 overlies the sidewalls210 in the second region. Gates 228 are formed overlying insulator layer226. In one embodiment, gates 228 may be coupled to the anode ofSchottky diode 212. Gates 228 comprises a conductive material such asdoped polysilicon, silicided polysilicon, a metal, or a combinationthereof. In general, MOS structures 230 form an enhancement regionadjacent to sidewalls 210 of mesa region 206 when diode 200 is forwardbiased. Conversely, MOS structures 230 form a depletion region adjacentto sidewalls 210 of mesa region 206 when diode 200 is reverse biased.

In the third region of diode 200 that resides below dashed line 224,p-type regions 232 are formed in sidewalls 210 of mesa region 206 apredetermined distance below the major surface 208 of mesa region 206.P-type regions 232 are formed in mesa region 206 a predetermineddistance below major surface 208 of mesa region 206 adjacent tosidewalls 210. A p-n diode 233 is formed comprising p-type regions 232and n-type mesa region 206. P-type regions 232 and n-type region mesaregion 206 are respectively an anode and cathode of p-n diode 233. Inone embodiment, p-type regions 232 are not coupled to a voltagepotential thereby the anode of p-n diode 233 can float. The p-typeregions 232 can also underlie the major surface of the trenches adjacentto sidewalls 210. The diode 233 may not be forward biased for conductingcurrent when diode 200 is forward biased. The floating p-type regions232 generate space charge regions that affect a current path in mesaregion 206 when diode 200 is reverse biased. Alternatively, p-typeregions 232 can be coupled to the anode of Schottky diode 212.

FIG. 3 illustrates a cross-sectional view showing current flow of thediode 200 under forward biased conditions in accordance with an exampleembodiment. Diode 200 comprises Schottky diodes 212 and the p-n diodes221 in parallel. As disclosed above, Schottky diodes 212 comprisebarrier metal 234 and mesa region 206. Diodes 221 comprise p-typeregions 220 and mesa region 206. In general, diode 200 conducts acurrent that couples through mesa region 206 to substrate 202 whenforward biased. The current path is both lateral and vertical in mesaregion 206. The forward bias current from diode 200 comprises currentfrom Schottky diode 212 and p-n diodes 221. The initial current pathfrom diode 200 flows laterally into mesa region 206. A lateral currentpath 306 corresponds to current flowing approximately parallel to majorsurface 208 of the mesa region 206 from Schottky diodes 212. Similarly,a portion of the current conducted by p-n diodes 221 will flow laterallyinto the mesa region 206. The current path of diode 200 changes from alateral current path to a vertical current path 308 for a majority ofthe current path through mesa region 206 to substrate 202. Verticalcurrent path 308 corresponds to current flow approximately parallel tosidewalls 210 of mesa region 206.

Ideally, to maximize power efficiency of diode 200 both the forwardvoltage drop across diode 200 and the resistance of the current path isminimized. In one embodiment, diode 200 includes Schottky diodes 212 tominimize the forward voltage drop when conducting current. The amount offorward voltage drop can be scaled by adjusting the total active area ofdiode 200 that comprises Schottky diodes 212 and p-n diodes 221. In oneembodiment, the current of diode 200 at low to medium current levels maybe principally carried by Schottky diodes 212. At high current levels,the current can be shared between Schottky diodes 212 and p-n diodes 221in parallel. Trade-offs exist, for example at some point increasing theactive area of diodes 212 and 221 may have diminishing returns in deviceefficiency as other factors such as switching losses can reduce thebenefit as the device size is increased.

In general, MOS structures 214 and 230 further enhance the performanceof diode 200 under forward biased conditions by effectively lowering theresistivity of mesa region 206. The gates of MOS structures 214 and 230are coupled to the anode of diode 200. In the example, a positive anodevoltage of diode 200 is applied to the gates 218 and 228 respectively ofMOS structures 214 and 230. Enhancement regions can be formed in mesaregion 206 by MOS structures 214 and 230. The active method of reducingthe resistivity of the current path of diode 200 in mesa region 206 hasthe further benefit of having little or no effect on the breakdowncharacteristics of diode 200 under reverse biased conditions.

More specifically, MOS structure 214 overlies major surface 208 of mesaregion 206. An enhancement region 304 is formed underlying insulatorlayer 216 in mesa region 206 under forward biased conditions of diode200. Enhancement region 304 has a lower resistivity than the adjacentareas of mesa region 206. Current from diode 200 takes a path of leastresistance while in lateral current path 306. Thus, the resistive pathis lowered for current being conducting laterally from sidewalls 210 ofmesa region 206 by Schottky diodes 212 and p-n diodes 221.

MOS structures 230 are a predetermined distance below the major surface208 of mesa region 206. In one embodiment, MOS structures 230 arebetween p-type regions 220 and p-type regions 232 adjacent to sidewalls210 of mesa region 206. A positive voltage is applied to gates 228 whendiode 200 is forward biased. An enhancement region 302 can be formedadjacent to insulator layer 226 along the sidewalls 210 of mesa region206 when diode 200 is forward biased. Enhancement region 302 has a lowerresistivity than the adjacent areas within mesa region 206. Current fromdiode 200 takes this path of least resistance while in the verticalcurrent path 308. Thus, the resistive path is lowered for current beingconducting vertically within mesa region 206 by MOS structures 230. Thecurrent path can spread out within mesa region 206 and in the cathoderegion 204 thereby further reducing the current density per unit area.

FIG. 4 illustrates a cross-sectional view of a pinch-off region 402 anda pinch-off region 404 when the diode 200 is reverse biased inaccordance with an example embodiment. Diode 200 can be designed tobreakdown above a predetermined voltage. Operation of diode 200 istypically maintained below the specified breakdown voltage of thedevice. The improved leakage current characteristic of diode 200 underreverse biased conditions is a contributor to diode 200 being powerefficient and having a smaller silicon footprint. The structure of diode200 reduces or maintains a low leakage current level over anon-breakdown reverse bias voltage range of the device. In general,multiple structures are placed in mesa region 206 that restrict thecurrent path of diode 200 under reverse biased conditions to reduceleakage current. In the example, the multiple structures comprise MOSstructures 214 and 230, and diodes 212, 221, and 233. Moreover, thecurrent path becomes more restricted as the reverse bias voltageincreases thereby lowering or reversing a rate of change in leakagecurrent as diode 200 approaches breakdown. The multiple structuresformed in mesa region 206 allow the performance to be improved in bothforward and reverse biased conditions. More specifically, the individualstructures can be tailored to optimize performance of diode 200 overspecific operating ranges or conditions.

In the example disclosed herein, the regions of diode 200 defined bydashed lines 222 and 224 each contribute to reducing leakage current.MOS structure 214, Schottky diode 212, and diode 221 formed in mesaregion 206 are shown in the illustration. Leakage current can be reducedby actively modifying the current path when diode 200 is reverse biased.In addition, p-type regions 220 provide leakage current reduction bybeing formed adjacent to and bounding Schottky diodes 212. In oneembodiment, leakage current is reduced by constriction or pinching-offthe current path through mesa region 206. The pinched-off current pathin mesa region 206 is reduced by space charge or depletion regions ofMOS structure 214, Schottky diode 212, and diode 221. Typically, thevolume occupied by the space charge or depletion region increases withreverse bias voltage of diode 200 thereby restricting the lateral andvertical current path. This corresponds well with diode 200 simulatedcharacteristics where the rate of change of diode 200 leakage current isreduced with respect to prior art diodes thereby providing a lower lowleakage current over an entire reverse bias operating range of thedevice.

Similar to diode 200 under forward biased conditions, leakage current isconducted in both lateral and vertical paths within mesa region 206under reverse biased conditions. As disclosed above, the leakage currentof diode 200 can be reduced by restricting the area of the lateral andvertical current path by depletion or space charge regions generated byMOS structure 214, Schottky diodes 212, and p-n diodes 221 when diode200 is reverse biased. A depletion region 410 that supports thepinch-off region 402 of a lateral leakage current path under reversebiased condition of diode 200 is produced by MOS structure 214. Asmentioned previously, gate 218 of MOS structure 214 is coupled to theanode of diode 200. The reverse bias voltage applied to gate 218 of MOSstructure 214 depletes mesa region 206 underlying insulator layer 216forming depletion region 410. The depletion region 410 and pinch-offregion 402 of the lateral current path is bounded by dashed line 416. Arestriction of pinch-off regions 402 can be produced by Schottky diodes212 when diode 200 is reverse biased. Schottky diodes 212 form spacecharge regions 412 in mesa region 206 that supports the pinch-offregions 402 when reverse biased thereby restricting the lateral currentpath. Dashed line 420 bounds space charge regions 412 and pinch-offregions 402. Finally, a space charge region 414 that supports furtherrestriction of pinch-off region 402 of the lateral current path isgenerated by the p-n diodes 221. Diodes 221 are coupled in parallel withthe Schottky diode 212. The space charge regions 414 are bounded frompinch-off region 402 by dashed line 418. The portion of space chargeregion 414 of diode 221 in proximity to major surface 208 of mesa region206 restricts pinch-off region 402 of the lateral current path. Thus,three space charge or depletion regions 410, 412, and 414 under reversebias conditions of diode 200 reduce the lateral current path asindicated by pinched-off regions 402 thereby reducing the leakagecurrent of diode 200. The pinch-off of the lateral current pathincreases with rising reverse bias voltage across diode 200 to reducethe rate of change of leakage current with reverse bias voltage.

In general, a vertical leakage current path in mesa region 206 underboth forward biased and reverse biased conditions are restricted bydiodes 221. P-type regions 220 of diode 221 form a neck within mesaregion 206. The vertical current path is further restricted when diode200 is reverse biased by the space charge regions 414 generated bydiodes 221. The space charge regions 414 of diode 221 change thevertical conductive path similar to a Junction Field Effect Transistor(J-FET). The conductive path of a J-FET is controlled by the amount ofreverse-bias on p-n junctions adjacent to a J-FET channel. Morespecifically, increasing or decreasing the space charge region of aJ-FET respectively decreases or increases the cross-sectional area ofthe conductive channel. Similarly, p-n diodes 221 form a pinch-offregion 404 that is between the space charge regions 414 of diode 221thereby reducing the area of the vertical current path. A portion ofspace charge regions 414 and pinch-off region 404 is bounded by dashedline 418. The reduction or restriction of the vertical current paththrough mesa region 206 by the space charge regions of p-n diodes 221further reduces leakage current when diode 200 is reverse biased.

FIG. 5 illustrates a cross-sectional view of a pinch-off region 502 anda pinch-off region 504 when the diode 200 is reverse biased inaccordance with an example embodiment. The pinch-off regions 502 and 504further reduce leakage current by restricting the vertical leakagecurrent path through mesa region 206 at different depths therein. MOSstructures 230 and p-n diodes 233 respectively generate the pinch-offregions 502 and 504 in a vertical current path of mesa region 206 underreverse bias conditions of diode 200. The MOS structures 230 are at apredetermined distance from the major surface 208 of mesa region 206. Inone embodiment, MOS structures 230 are formed on a portion of sidewalls210 below p-type regions 220 and above p-type regions 232. Diodes 233are formed below MOS structures 230 in mesa region 206. A reverse biasvoltage applied to the anode of diode 200 is coupled to gates 228 of MOSstructures 230 thereby forming depletion regions 506 adjacent tosidewalls 210 that restrict the vertical current path. Pinch-off region502 is the portion of the vertical current path through mesa region 206that is restricted by depletion regions 506. The amount of depletiongenerated by MOS structures 230 corresponds to the doping density ofmesa region 206 and the voltage applied to the gate of MOS structures230. The depletion regions 506 and pinch-off region 502 is bounded bydashed line 510. The dashed lines 510 are below horizontal dashed line222 and above horizontal dashed line 224.

The vertical current path through mesa region 206 can be furtherrestricted by diodes 233 forming pinch-off region 504. In the example,p-n diodes 233 comprise p-type regions 232 and n-type mesa region 206.In one embodiment, the anodes of diodes 233 float and are not coupled toa voltage potential. Pinch-off region 504 is between the space chargeregions 508 of diodes 233. The space charge regions 508 and pinch-offregion 504 is bounded by dashed lines 512. The dashed lines 512 arebelow the horizontal dashed line 224. As shown, p-type regions 232 alsounderlie a major surface of the trenches etched to form mesa region 206.Pinch-off regions 502 and 504 support a reduction of leakage currentunder reverse bias conditions that restricts the vertical current pathas the current path enters into cathode 204. Below mesa region 206,cathode 204 continues for a predetermined distance until it couples tolow resistivity substrate 202. In cathode 204, the current path is notrestricted below mesa region 206 and the current can spread as itapproaches substrate 202.

Although disclosed as separate pinch-off regions, the proximity ofregions 402, 404, 502, and 504 can interact with one another. Morespecifically, adjacent pinch-off regions can affect or modify the amountof restriction that occurs. Simulations of diode 200 can determine theamount of interaction and the effect thereof. Another factor in theinteraction of the pinch-off regions can be the doping concentrationwithin mesa region 206. As mentioned previously, mesa region 206 canhave uniform doping or non-uniform doping. For example, ion implants canbe used to modify doping of mesa region 206 through the major surface208 and/or sidewalls 210. In one embodiment, cathode 204 of diode 200comprises an epitaxial layer formed overlying substrate 202. Mesa region206 is formed by removing portions of the epitaxial layer wherebytrenches are adjacent to sidewall 210. Alternatively, cathode 204 cancomprise more than one epitaxial layer. Each epitaxial layer may have adifferent doping concentration. Mesa region 206 can be formed to extendinto two or more epitaxial layers to provide different doping levels atdifferent depths and the corresponding devices formed therein.

In one example, the diode 200 was compared to a prior-art rectifyingdiode having a breakdown voltage of approximately 100 volts. Diode 200had a substantial reduction in leakage current for the same breakdownvoltage. As mentioned previously, trade-offs can be made to improveother performance characteristics of diode 200 while maintaining lowleakage current. For example, the leakage current of diode 200 wasmaintained at a value equivalent to other prior art diodes whileimproving other diode characteristics. For example, the lower leakagecurrent of diode 200 can be traded off by lowering the resistivity ofcathode 204 until the leakage current is approximately equal to priorart diodes. The lower resistivity resulted in a substantial reduction inforward operating voltage and the corresponding improvement in powerefficiency. Alternatively, by holding the leakage current and forwardoperating voltage similar to the prior art diodes, diode 200 could bereduced in area by 30% resulting in a substantial manufacturing costreduction.

FIGS. 6-11 illustrate at one stage of an example of an embodiment of amethod of forming a diode 600. Diode 600 may be similar to embodimentsof diode 200. FIG. 6 is a cross-sectional view of trenches formed inaccordance with example embodiment of diode 600. The diode 600 can havea reverse bias breakdown voltage exceeding a hundred volts whilecarrying amperes of current or tens of amperes of current when forwardbiased in a rectifier application. Disclosed herein is an example ofdiode 600 having a hundred voltage breakdown to illustrate the method.In general, the specific doping concentrations, resistivities, physicalparameters, and characteristics disclosed herein support the 100 voltbreakdown example. In one embodiment, a starting material comprises asubstrate 602 and epitaxial layers 604, 606, and 608. Substrate 602 is alow-resistivity n-type substrate. In the example, silicon substrate 602comprises 0.003 ohm-centimeter material having an n-type dopingconcentration of approximately 2.0 e¹⁹/cm³. The epitaxial layers 604,606, and 608 are n-type epitaxial layers each having differentresistivities. The epitaxial layers 604, 606, and 608 and the dopingconcentrations thereof support the breakdown voltage of diode 600. Inthe example, epitaxial layer 604 comprises an n-type layer ofapproximately 6.5-8.0 microns in depth. Epitaxial layer 604 has ann-type doping concentration range of approximately (2.5-4.5) e¹⁵/cm³.Epitaxial layer 606 overlies epitaxial layer 604. Epitaxial layer 606comprises an n-type layer of approximately 0.6-1.6 microns in depth.Epitaxial layer 606 has an n-type doping concentration of approximately1.0-2.0 e¹⁵/cm³. Epitaxial layer 608 overlies epitaxial layer 606.Epitaxial layer 608 comprises an n-type layer of approximately 0.5-1.0microns in depth. Epitaxial layer 608 has an n-type doping concentrationof approximately 4.0 e¹⁵/cm³-1.0 e¹⁶/cm³. Alternatively, a singleepitaxial layer can overlie substrate 602 as disclosed for the examplediode 200. The single epitaxial layer for a 100 v breakdown has a depthof approximately 7.0 microns. The single epitaxial layer has an n-typedoping concentration of approximately 4.7 e¹⁵/cm³ or comprises 1.0ohm-centimeter material.

An insulating layer is formed overlying epitaxial layer 608. In theexample, the insulating layer is a pad silicon dioxide layer 610 that isformed overlying a surface of epitaxial layer 608. Silicon dioxide layer610 can be formed having a thickness of approximately 0.1-0.2 microns.An insulating layer can then formed overlying silicon dioxide layer 610.In the example, the insulating layer can be a silicon nitride layer 612that is formed overlying pad silicon dioxide layer 610. In oneembodiment, silicon nitride layer 612 is formed approximately 2000angstroms thick. Photoresist is formed overlying silicon nitride layer612. The photoresist is patterned and exposed such that portions ofsilicon nitride layer 612 are removed while remaining photoresistprotects underlying material. The exposed portions of silicon nitridelayer 612 correspond to regions where material may be removed.

The exposed portions of silicon nitride layer 612 are removed exposingsilicon dioxide layer 610. Similarly, exposed portions of silicondioxide layer 610 are removed in non-photoresist protected areas therebyexposing epitaxial layer 608. Trenches 616 are formed by removingmaterial from exposed epitaxial layer 608. In the example, a trench etchmay be performed that etches through epitaxial layer 608 and partiallyinto epitaxial layer 606 exposing a major surface 618 in each trench616. Mesa regions are formed between trenches 616 having sidewalls 614.In one embodiment, the trench etch leaves a slope on sidewalls 614. Thephotoresist can be removed after trenches 616 have been etched exposingremaining portions of silicon nitride layer 612. As shown, more than onemesa region can be formed by the trench etch. Mesa regions are theremaining portions of epitaxial layers 608 and 606 between trenches 616.In the example of the 100 volt diode, the width of a mesa region betweentrenches 616 can be approximately 1.5-3.0 microns wide. Trenches can beformed in a range of approximately 1.0 microns to 2.0 microns from themajor surface of the mesa regions. The subsequently formed diodes ofeach mesa region disclosed herein can be coupled in parallel to form onelarge diode capable of handling high currents with a low forward voltagedrop.

FIG. 7 illustrates diode 600 at another stage of formation according toan example of the cross-sectional view of the preparation of thesidewalls 614. An insulating layer is formed overlying sidewalls 614 andmajor surface 618 of each trench 616. In the example, a first insulatinglayer is a silicon dioxide layer (not shown) that is formed on theexposed sidewalls 614 and major surface 618 of each trench 616. In oneembodiment, the silicon dioxide layer can be a sacrificial oxideapproximately 1000 angstroms thick. The first silicon dioxide layer isthen sacrificed or removed thereby leaving the sidewalls 614 and majorsurface 618 of each trench 616 exposed. An insulating layer can then beformed overlying sidewalls 614 and major surface 618 of each trench 616.In the example, the insulating layer can be a silicon dioxide layer 702.In one embodiment, the silicon dioxide layer 702 can be a trench lineroxide approximately 50 angstroms thick that overlies sidewalls 614 andmajor surface 618 of each trench 616. An insulating layer can then beformed overlying silicon nitride layer 612 and silicon dioxide layer702. In the example, the insulating layer can be a silicon nitride layer704. In one embodiment, the silicon nitride layer 704 is 500 angstromsthick. The silicon nitride layer 704 couples to the silicon nitridelayer 612. The combined thickness of silicon nitride layers 704 and 612overlying the major surface of each mesa region is approximately 2500angstroms thick. The silicon nitride layer 704 overlies silicon dioxidelayer 702 on sidewalls 614 and major surface 618 of each trench 618.

FIG. 8 illustrates diode 600 at another stage of formation according toan example of the cross-sectional view of the preparation of extendingtrenches 616. The silicon nitride layer 704 can be preferentiallyremoved overlying each mesa region and the major surfaces of each trench616. In the example, an anisotropic etch can be performed on siliconnitride layer 704 such that silicon nitride is removed overlying majorsurface 618 of each trench 616 and removed from the insulator stackcomprising silicon nitride layer 704 and silicon nitride layer 612. Notethat only a portion of the silicon nitride is removed from the combinedlayers 704 and 612 overlying the mesa regions and thus at least aportion of silicon nitride layer 612 remains. Moreover, a portion ofsilicon nitride layer 704 overlying silicon dioxide layer 702 onsidewalls 614 remains after the anisotropic etch due to the preferentialremoval process.

The removal of silicon nitride layer 704 exposes silicon dioxide layer702 overlying major surface 618 of each trench 616. The exposed silicondioxide layer 702 can then be removed. In the example, an oxide etchremoves exposed silicon dioxide layer 702 thereby exposing major surface618 of each trench 616. Material can be removed from major surface 618of epitaxial layer 606. Trenches 616 are extended to an increased depthby removing epitaxial material. In the example, a recess etch can beperformed to remove epitaxial material in each trench 616. In oneembodiment, the recess etch etches through epitaxial layer 606 andpartially into epitaxial layer 604.

An insulating layer (not shown) is then formed on exposed portions ofsidewalls 614 and major surface 808 of trenches 616. In the example, theinsulating layer comprises silicon dioxide. The silicon dioxide layerformed on the exposed portions of sidewalls 614 and major surface 808 oftrenches 616 can be a sacrificial oxide that is subsequently removed. Aninsulating layer can then be formed on the exposed portions of sidewalls614 and major surface 808 after removing the sacrificial oxide layer. Inthe example, the insulating layer can be formed as a silicon dioxidelayer 804. In one embodiment, a wet oxidation process can be used togrow silicon dioxide layer 804 having thickness of approximately1500-3000 angstroms. Mesa regions 802 comprise the epitaxial region 608,epitaxial region 606, and a portion of epitaxial region 604 betweentrenches 616 and defined by the trench etch and the recessed trench etchdisclosed above.

Dopant can be placed underlying silicon dioxide layer 804 that willsubsequently form a doped region. In the example, the dopant is p-type.A blanket boron implant can be used to place the p-type dopant. Theboron implant penetrates portions of silicon dioxide layer 804 but notareas protected by silicon nitride layers 612 and 704. In general,silicon nitride layer 612 and 704 form a mask to prevent dopant frombeing placed in sidewalls 614 and below the major surface of mesa region802 from being doped. The boron implant underlying silicon dioxide layer804 is then annealed forming p-type regions 806. The p-type regions 806correspond to p-type regions 232 and diode 233 of diode 200 disclosedherein. P-type regions 806 form p-n junctions with epitaxial layer 604where the space charge regions of the diodes can pinch-off or restrictthe vertical current path through mesa region 802 under reverse biasconditions of diode 600. As disclosed above, mesa regions 802 compriseepitaxial layer 608, epitaxial layer 606, and a portion of epitaxiallayer 604 between trenches 616 each having a different dopingconcentration. Thus, the mesa regions 802 have a non-uniform dopingconcentration in the embodiment. Furthermore, the doping concentrationwithin each epitaxial layer can be uniform or non-uniform.

In the example of a 100 volt diode, p-type regions 806 are formed inepitaxial layer 604 having a doping concentration of (2.5-4.5) e¹⁵/cm³.The anneal process diffuses p-type regions 806 to a depth approximately0.25-0.3 microns vertically below silicon dioxide layer 804. P-typeregions 806 extend approximately 0.2-0.25 microns laterally intoepitaxial layer 604 from a boundary of silicon dioxide layer 804 inproximity to mesa region 802.

FIG. 9 illustrates diode 600 at another stage of formation according toan example of the cross-sectional view having partially filled trenches616. In general, a selective removal of insulating layers is disclosedfollowed by a placement of a conductive material in trenches 616. Thesilicon nitride layers 612 and 704 respectively overlying silicondioxide layer 610 and silicon dioxide layer 702 are removed. In oneembodiment, a wet strip can be used to remove silicon nitride layers 612and 704. The removal of silicon nitride layers 612 and 704 exposes anunderlying insulating layer. In the embodiment, the wet strip exposessilicon dioxide layer 610 and silicon dioxide layer 702. A material isthen placed in trenches 616. In the example, the material can beelectrically conductive and partially fill trenches 616. In oneembodiment, the conductive material can be a layer of polysilicon. Thelayer of polysilicon overlies silicon dioxide layer 610 and partiallyfills trenches 616. The layer of polysilicon is subsequently removedoverlying silicon dioxide layer 610 whereby polysilicon 900 remains intrenches 616. Polysilicon 900 can be doped polysilicon or doped with adopant such as boron after being formed. Further material frompolysilicon 900 can be removed in a subsequent step. Polysilicon 900 canbe formed to a predetermined height below the major surface of mesaregions 802 in the trenches 616. The predetermined height of polysilicon900 is positioned to form and locate p-type regions adjacent to aportion of sidewalls 614 corresponding to p-type regions 220 of FIG. 2.In one embodiment, the polysilicon 900 can be above silicon dioxidelayer 804 overlying sidewalls 614 of mesa regions 802.

In the example of the 100 volt diode, the polysilicon 900 is placedapproximately 0.25-0.35 microns above silicon dioxide layer 804. The0.25-0.35 micron portion of polysilicon 900 above silicon dioxide layer804 overlies silicon dioxide layer 702. The remaining polysilicon 900 intrenches 616 overlie silicon dioxide layer 804. The major surface ofpolysilicon 900 is approximately 0.80 microns below the major surface ofmesa regions 802. In one embodiment, the portion of polysilicon 900 thatoverlies silicon dioxide layer 702 can be aligned with epitaxial layer606 having a doping concentration of 1.0-2.0 e¹⁵/cm³.

FIG. 10 illustrates diode 600 at another stage of formation according toan example of the cross-sectional view of p-type regions 1000 formed inmesa regions 802. In general, a dopant can be placed adjacent to aportion of sidewalls 614 of mesa region 802 to form p-type regions 1000.As mentioned previously, polysilicon 900 can be made conductive by adopant placed therein. A p-type dopant such as boron can be placed inpolysilicon 900. Thus, polysilicon 900 can be a source of the dopant forforming the p-type regions 1000 adjacent to sidewalls 614. In oneembodiment, the p-type dopant in polysilicon 900 diffuses into mesaregion 802 in a controlled fashion. For example, a timed thermal cyclecan control the amount of diffusion of dopant into mesa region 802. Thepath of diffusion is the polysilicon 900 that overlies silicon dioxidelayer 702 overlying sidewalls 614 thereby localizing the dopant at thepredetermined distance below the major surface of mesa region 802. Ingeneral, dopant diffuses into epitaxial layer 606 forming p-type regions1000. Subsequent thermal steps in the process flow can increase outdiffusion of p-type region 1000 in mesa region 802. P-type regions 1000can extend into epitaxial layer 608 and epitaxial layer 604. P-typeregions 1000 correspond to p-type regions 220 of FIG. 2. P-type regions1000 can form a p-n diode with epitaxial layers 608, 606, and 604 thatmay pinch-off or restrict the lateral and vertical current path throughmesa region 802 under reverse bias conditions of diode 600. Theselection of the characteristics of epitaxial layer 608 can be used tooptimize the performance of diode 600 in conjunction with the p-njunction comprising p-type regions 1000.

In the example of the 100 volt diode, p-type regions 1000 are formed ina major portion of epitaxial layer 606 but can also be partially formedin epitaxial layers 608, epitaxial layer 604, or both. The epitaxiallayer 606 is approximately 1.0-1.5 microns in depth. P-type regions 1000have a vertical width of approximately 0.65-0.85 microns in epitaxiallayer 606 adjacent to sidewalls 614. P-type regions 1000 extend intomesa region 802 approximately 0.4-0.45 microns from sidewalls 614 ofmesa region 802. P-type regions 1000 form a p-n diode with mesa region802. P-type regions 1000 form a neck that reduces the vertical currentpath within mesa region 802 by 0.80-0.90 microns. The current path isfurther reduced by the space charge region of the p-n junction asdisclosed herein.

FIG. 11 illustrates diode 600 at another stage of formation according toan example of the cross-sectional view of Schottky diodes being formed.In general, an insulating layer is removed on a portion of sidewalls 614that exposes mesa region 802. A barrier metal 1100 can be placed on theexposed portion of sidewalls 614 to form Schottky diodes. The barriermetal 1100 also couples to p-type regions 1000 and polysilicon 900.Prior to the placement of barrier metal 1100, a polysilicon recess etchcan be performed that removes some polysilicon or all of the polysilicon900 in trenches 616. The recess etch increases a distance of the majorsurface of polysilicon 900 in trenches 616 from the major surface ofmesa regions 802. In one embodiment, the recess etch leaves polysilicon900 overlying silicon dioxide layer 804 and overlying a portion ofsilicon dioxide layer 702. Although disclosed herein that thepolysilicon 900 includes a boron dopant, the polysilicon 900 can also bea phosphorous-doped polysilicon.

An insulating layer can be removed on a portion of sidewalls 614 toexpose mesa region 802. In one embodiment, a sidewall silicon dioxidewet strip removes silicon dioxide layer 702. A conductive material isthen placed on the exposed portion of sidewalls 614 and to fill in areaswhere silicon dioxide layer 702 was removed. In one embodiment, theconductive material is barrier metal 1100 that can be formed on thesidewalls 614 of mesa regions 802. Schottky diodes are formed with thebarrier metal 1100 as an anode and mesa region 802 as the cathode. Thebarrier metal 1100 can overlie epitaxial layer 608 or epitaxial layers608 and 606 on sidewalls 614. The barrier metal 1100 may overlie andcouple to p-type regions 1000. The Schottky diodes correspond toSchottky diodes 212 of FIG. 2.

In the example of the 100 volt diode, the cathode of the Schottky diodesis primarily formed in epitaxial layer 608 of mesa region 802 but canalso be formed in a portion of epitaxial layer 606. The epitaxial layer608 has an n-type doping concentration of 4.0 e¹⁵/cm³-1.0 e¹⁶/cm³. Inone embodiment, the Schottky diodes are formed below the major surfaceof mesa region 802 and are bounded by p-type regions 1000.

In general, diode 600 comprises the Schottky diodes in parallel with thep-n diodes formed by p-type regions 1000 and epitaxial layer 606. Asillustrated, the Schottky diodes are formed on sidewalls 614 adjacent tothe major surface of mesa regions 802. The width of a Schottky diode isdefined by the barrier metal contact area between the major surface andp-type regions 1000. In the example of the 100 volt diode, the width ofthe barrier metal 1100 is approximately 0.5-1.4 microns. The active areaof the Schottky diode on each sidewall 614 is the width times the lengthof the Schottky barrier metal contact area on each mesa region 802. Thelength is selected for the current carrying requirement of theapplication. An example of barrier metals used to form the Schottkydiodes are Cr, Ti, Ni, Pt, W, Ta, Co, and Hf to name but a few that forma silicide with silicon each having different barrier heights.

A conductive material is placed in trenches 616. In one embodiment,tungsten is placed in trenches 616 to form tungsten plugs 1104. Amaterial removal step or planarization step can be used to removetungsten material such that a major surface of tungsten plugs 1104 isapproximately planar to the major surface of the die. The conductivematerials comprising tungsten plugs 1104, barrier metal 1100, p-typeregions 1000, and polysilicon 900 are coupled in common. In the example,p-type regions 806 are left floating. Alternatively, p-type regions 806can be coupled to the anode of diode 600.

MOS structures 1106 are formed adjacent to sidewalls 614 comprisingpolysilicon 900, silicon dioxide layer 804 and mesa region 802 thatrespectively are the gate, insulating layer, and substrate of thedevice. The gate of MOS structures 1106 are coupled to the anode ofdiode 600. The MOS structures 1106 correspond to MOS structures 230 ofFIG. 2. MOS structures 1106 are bounded by p-type regions 1000 andp-type regions 806. In one embodiment, the gate width of MOS structures1106 the distance between p-type region 1000 and 806 on sidewalls 614.The substrate of MOS structures 1106 comprises epitaxial layer 606,epitaxial layer 604, or both. In the example of the 100 volt diode, theepitaxial layer 606 has an n-type doping concentration of approximately1.0-2.0 e¹⁵/cm³ and the epitaxial layer 604 has a doping concentrationof approximately 2.5-4.5 e¹⁵/cm³. Epitaxial layers 606 and 604 supportan enhancement region being formed in epitaxial layer 606 when diode 600is forward biased. Conversely, epitaxial layers 606 and 604 support adepletion region being formed in the substrate of MOS structures 1106when diode 600 is reverse biased.

A conductive material is formed overlying the insulating layer on themajor surface of mesa regions 802. In one embodiment, the conductivematerial is formed on silicon dioxide layer 610. The conductive materialcan be patterned to form a conductive layer 1110. The conductive layer1110 can be doped polysilicon, silicide, or metal. The conductive layer1110 is the gate of a MOS structure 1108. MOS structure 1108 is formedoverlying the major surface of mesa regions 802 and comprises conductivelayer 1110, silicon dioxide layer 610 and mesa region 802 thatrespectively are the gate, insulating layer, and substrate of thedevice. In one embodiment, the conductive layer 1110 is coupled to theanode of diode 600 and tungsten plugs 1104 by a subsequent conductivelayer or layers. The MOS structure 1108 corresponds to the MOS structure214 described in FIG. 2.

In the example, the substrate of MOS structure 1108 is epitaxial layer608 of mesa region 802. In the example, the epitaxial layer 608 has ann-type doping concentration of approximately 4.0 e¹⁵/cm³-1.0 e¹⁶/cm³.The width of the gate of MOS structure 1108 is approximately 1.5-3.0microns that corresponds to the width of mesa region 802. The dopingconcentration supports an enhancement region being formed in epitaxiallayer 608 when diode 600 is forward biased. Conversely, a depletionregion can be formed in epitaxial layer 608 when diode 600 is reversebiased. The MOS structure 1108 improves performance of diode 600 in bothforward and reverse bias operation.

Thus, a device manufacturing process is disclosed that utilizes fewmasking and processing steps that creates the device structure for diode600. The diode 600 comprises a Schottky diode and a p-n diode inparallel. The Schottky diode and the p-n diode are formed in thesidewalls 614 of mesa regions 802. The Schottky diode carries a majorityof the current under forward biased conditions at low to mid currentlevels of the application whereby the p-n diode increasingly carries aportion of the current at higher current levels. The low forward voltagedrop of the Schottky diode reduces power dissipation of diode 600. TheMOS structures 1106 and 1108 form enhancement regions when diode 600 isforward biased. The enhancement regions of MOS structures 1106 and 1108lower the resistivity of the current path thereby improving deviceefficiency.

Diode 600 under reverse bias conditions generates four pinch-off regionsthat constrict the lateral and vertical current path in mesa region 802.The pinch-off regions reduce the leakage current of diode 600. The diode600 can also be formed having fewer or more pinch-off regions withinmesa region 802 using the methodology disclosed herein. Similarly, thediode 600 can also be formed having more or less devices that reduce theresistivity of the current paths under forward bias operation using themethodology disclosed herein.

Thus, the description of the invention is merely exemplary in natureand, thus, variations that do not depart from the gist of the inventionare intended to be within the scope of the embodiments of the presentinvention. Such variations are not to be regarded as a departure fromthe spirit and scope of the present invention.

As the claims hereinafter reflect, inventive aspects may lie in lessthan all features of a single foregoing disclosed embodiment. Thus, thehereinafter expressed claims are hereby expressly incorporated into thisDetailed Description of the Drawings, with each claim standing on itsown as a separate embodiment of an invention. Furthermore, while someembodiments described herein include some but not other featuresincluded in other embodiments, combinations of features of differentembodiments are meant to be within the scope of the invention, and formdifferent embodiments, as would be understood by those skilled in theart.

What is claimed is:
 1. A method of forming a semiconductor devicecomprising the steps of: forming trenches to a first depth in asemiconductor substrate to form a mesa region of a first conductivitytype; placing dopant of a second conductivity type into a sidewall ofthe mesa region to form a first region of the second conductivity type,where the dopant is located a first predetermined distance below a majorsurface of the mesa region; forming a barrier metal overlying a portionof the sidewall of the mesa region to form a Schottky diode; and forminga MOS structure overlying the major surface of the mesa region, where agate of the MOS structure is coupled to the barrier metal.
 2. The methodof claim 1 further including the steps of: forming an insulating layeroverlying the major surface of the mesa region; forming an insulatinglayer overlying sidewalls of the mesa region to a first depth; exposingmajor surfaces of the trenches; forming the trenches to a second depth;forming an insulating layer overlying exposed portions of sidewalls ofmesa region from at least the first depth to the second depth and majorsurfaces of the trenches; placing dopant of the second conductivity typeunderlying major surfaces of the trenches; and annealing the dopant toform second regions of the second conductivity type underlying the majorsurface of each trench.
 3. The method of claim 1 where the step ofplacing dopant of a second conductivity type into sidewalls of the mesaregion to form first regions of the second conductivity type furtherincludes the steps of: placing polysilicon in the trenches of the firstdepth; and diffusing dopant in the polysilicon through an insulatinglayer overlying sidewalls of the trenches above the first depth wherethe polysilicon aligns with the first predetermined distance below themajor surface of the mesa region.
 4. The method of claim 3 where thestep of forming the barrier metal overlying a portion of the sidewall ofthe mesa region to form a Schottky diode further includes the steps of:removing the insulating layer overlying the sidewall of the mesa regionto the first depth; and forming the barrier metal overlying the sidewallof the mesa region where the barrier metal couples to the mesa region,dopant of the second conductivity type at the first predetermineddistance, and the polysilicon in the trenches.
 5. The method of claim 4where the step of placing polysilicon in the trenches further includes astep of providing doped polysilicon or placing dopant into thepolysilicon.
 6. The method of claim 4 further including a step ofproviding the semiconductor substrate having one or more epitaxiallayers overlying the semiconductor substrate, and where the step offorming the trenches includes forming the trenches in at least oneepitaxial layer.
 7. A method for forming semiconductor devicecomprising: providing a substrate of a first conductivity type andhaving a mesa region of the first conductivity type, where the mesaregion has a major surface and sidewalls; forming a first diodecomprising a first region of a second conductivity type a firstpredetermined distance from the major surface of the mesa region andadjacent to a sidewall of the mesa region; forming a first MOS structureoverlying the major surface of the mesa region; and forming a Schottkydiode comprising an anode and a cathode where the anode of the Schottkydiode overlies a portion of at least one sidewall of the mesa region andwhere the cathode of the Schottky diode is the mesa region, where theanode of the Schottky diode is configured to couple to the first region.8. The method of claim 7 where forming the first MOS structure includesforming a gate of the first MOS structure that is configured to coupleto the anode of the Schottky diode.
 9. The method of claim 7 whereforming the Schottky diode includes forming the anode comprising abarrier metal adjacent to the major surface of the mesa region.
 10. Themethod of claim 9 where forming the Schottky diode includes forming aportion of the anode overlying a portion of the first region of thesecond conductivity type.
 11. The method of claim 7 further includingforming a second MOS structure overlying a portion of the sidewall ofthe mesa region at a second predetermined distance below the majorsurface of the mesa region.
 12. The method of claim 11 where forming thesecond MOS structure includes forming a gate of the second MOS structureconfigured to couple to the anode of the Schottky diode.
 13. The methodof claim 11 further including forming a second diode comprising a secondregion of the second conductivity type a third predetermined distancefrom the major surface of the mesa region.
 14. The method of claim 13where forming the first diode, the second MOS structure, and seconddiode includes forming the first diode, the second MOS structure, andthe second diode such that the first predetermined distance is above thesecond predetermined distance and the second predetermined distance isabove the third predetermined distance.
 15. The method of claim 7 whereproviding the semiconductor substrate includes providing the substratehaving a uniformly doped mesa region.
 16. The method of claim 7 whereproviding the semiconductor substrate includes providing the substratehaving a non-uniformly doped mesa region.
 17. A method for forming asemiconductor device comprising: providing a substrate of a firstconductivity type; forming a mesa region in the substrate, where themesa region comprises the first conductivity type and has a majorsurface and sidewalls; forming a Schottky diode comprising an anode anda cathode where the anode of the Schottky diode overlies a portion of asidewall of the mesa region, and where the cathode of the Schottky diodecomprises the mesa region; forming a first MOS structure overlying themajor surface of the mesa region; and forming a second MOS structureoverlying a another portion of the sidewall of the mesa region and at afirst predetermined distance below the major surface of the mesa. 18.The method of claim 17 further including a forming a first diodecomprising a first region of a second conductivity type at a secondpredetermined distance from the major surface of the mesa region andadjacent to the sidewall of the mesa region where the first region iscoupled to the anode of the Schottky diode.
 19. The method of claim 18where forming the first MOS structure includes forming the first MOSstructure having a first gate coupled to the anode of the Schottkydiode, and where forming the second MOS structure includes forming thesecond MOS structure having a second gate coupled to the anode of theSchottky diode.
 20. The method of claim 19 further including forming asecond diode comprising a second region of the second conductivity typea third predetermined distance from the major surface of the mesa regionand adjacent to the sidewall of the mesa region, where the secondpredetermined distance is above the first predetermined distance, andwhere the first predetermined distance is above the third predetermineddistance.